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| a FEATURES Throughput 570 kSPS (Warp Mode) 500 kSPS (Normal Mode) 16 Bits Resolution Analog Input Voltage Range: 0 V to 2.5 V No Pipeline Delay Parallel and Serial 5 V/3 V Interface SPITM/QSPITM/MICROWIRETM/DSP Compatible Single 5 V Supply Operation Power Dissipation 77 mW Typical @ 444 kSPS (Impulse Mode) 21 W @ 100 SPS Power-Down Mode: 7 W Max Package: 48-Lead Quad Flat Pack (LQFP) or 48-Lead Frame Chip-Scale Pack (LFCSP) Pin-to-Pin Compatible with PulSAR ADCs APPLICATIONS Data Acquisition Instrumentation Digital Signal Processing Spectrum Analysis Medical Instruments Battery-Powered Systems Process Control IN+ IN- 16-Bit, 570 kSPS Low Cost CMOS ADC AD7650* FUNCTIONAL BLOCK DIAGRAM AVDD AGND REF REFGND DVDD DGND OVDD OGND SWITCHED CAP DAC SERIAL PORT SER/PAR BUSY PARALLEL 16 INTERFACE CLOCK PD RESET CONTROL LOGIC AND CALIBRATION CIRCUITRY DATA[15:0] CS RD OB/2C AD7650 WARP IMPULSE CNVST GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7650 is a 16-bit, 570 kSPS, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power supply. The part contains a high-speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. It features a very high sampling rate mode (Warp) and, for asynchronous conversion rate applications, a fast mode (Normal) and, for low power applications, a reduced power mode (Impulse) where the power is scaled with the throughput. It is fabricated using Analog Devices' high-performance, 0.6 micron CMOS process and is available in a 48-lead LQFP or in a tiny 48-lead Chip Scale package with operation specified from -40C to +85C. 1. Fast Throughput The AD7650 is a 570 kSPS, charge redistribution, 16-bit SAR ADC. 2. Single-Supply Operation The AD7650 operates from a single 5 V supply. In impulse mode, its power dissipation decreases with the throughput from 77 mW at 444 kSPS throughput to, for instance, only 21 W at a 100 SPS throughput. It consumes 7 W maximum when in power-down. 3. Serial or Parallel Interface Versatile parallel or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic. *Patent pending. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 AD7650-SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise Full-Scale Error2 Unipolar Zero Error2 Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Condition (-40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Min 16 Typ Max Unit Bits VREF +3 +0.5 V V V dB A VIN+ - VIN- VIN+ VIN- fIN = 10 kHz 570 kSPS Throughput 0 -0.1 -0.1 62 7 See Analog Input Section In Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode 1 0 0 -6 15 0.7 1.75 570 1 2 500 2.25 444 +6 0.12 25 s kSPS ms s kSPS s kSPS LSB1 Bits LSB % of FSR LSB3 LSB dB4 dB dB dB dB dB MHz ns ps rms ns V A REF = 2.5 V AVDD = 5 V 5% fIN = 100 kHz fIN = 100 kHz fIN = 45 kHz fIN = 100 kHz fIN = 100 kHz -60 dB Input, fIN = 100 kHz 5 3 86 98 -98 -96 86 30 18 2 5 Full-Scale Step 2.3 2.5 115 250 AVDD - 1.85 REFERENCE External Reference Voltage Range External Reference Current Drain 570 kSPS Throughput DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD ISINK = 1.6 mA ISOURCE = -500 A -0.3 2.0 -1 -1 +0.8 OVDD + 0.3 +1 +1 V V A A Parallel or Serial 16-Bit Delay Conversion Results Available Immediately after Completed Conversion 0.4 OVDD - 0.6 V V 4.75 4.75 2.7 5 5 5.25 5.25 5.25 V V V REV. 0 -2- AD7650 AD7650 Parameter POWER SUPPLIES (continued) Operating Current5 AVDD DVDD6 OVDD6 Power Dissipation6 Condition 570 kSPS Throughput 15.5 4.2 100 570 kSPS Throughput5 444 kSPS Throughput7 100 SPS Throughput7 In Power-Down Mode8 TMIN to TMAX -40 115 77 21 7 +85 mA mA A mW mW W W C Min Typ Max Unit TEMPERATURE RANGE9 Specified Performance NOTES 1 LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 V. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 Tested in warp mode. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 5 In warp mode. 6 Tested in parallel reading mode. 7 In impulse mode. 8 With all digital inputs forced to OVDD or OGND respectively. 9 Contact factory for extended temperature range. Specifications subject to change without notice. TIMING SPECIFICATIONS Parameter (-40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 2 10 1.5/1.75/2 250 10 Min 5 1.75/2/2.25 Typ Max Unit ns s ns s ns ns s ns ns REFER TO FIGURES 8 AND 9 Convert Pulsewidth Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read After Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time RESET Pulsewidth REFER TO FIGURES 10, 11 AND 12 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time REFER TO FIGURES 13 AND 14 (Master Serial Interface Modes)2 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay2 CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay Internal SCLK Period Internal SCLK HIGH (INVSCLK Low)3 Internal SCLK LOW (INVSCLK Low)3 SDOUT Valid Setup Time SDOUT Valid Hold Time REV. 0 Note 1 30 1.5/1.75/2 t10 t11 t12 t13 45 5 1.5/1.75/2 s ns ns ns 40 15 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 -3- 10 10 10 25/275/525 4 40 30 9.5 4.5 3 ns ns ns ns ns ns ns ns ns ns 75 AD7650 TIMING SPECIFICATIONS (continued) Parameter REFER TO FIGURES 13 AND 14 (continued) SCLK Last Edge to SYNC Delay CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read After Convert (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay REFER TO FIGURES 15 AND 16 (Slave Serial Interface Modes)2 External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW Symbol t24 t25 t26 t27 t28 t29 t30 Min 3 10 10 10 2.75/3/3.25 1/1.25/1.5 50 ns ns ns s s ns Typ Max Unit t31 t32 t33 t34 t35 t36 t37 5 3 5 5 25 10 10 16 ns ns ns ns ns ns ns NOTES 1 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3 If the polarity of SCLK is inverted, the timing references of SCLK are also inverted. Specifications subject to change without notice. 1.6mA IOL TO OUTPUT PIN 1.4V CL 60pF* 2V 500 A IOH 0.8V *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. tDELAY 2V 0.8V tDELAY 2V 0.8V Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF Figure 2. Voltage Reference Levels for Timing -4- REV. 0 AD7650 ABSOLUTE MAXIMUM RATINGS 1 Analog Inputs IN+2, REF, IN-, REFGND . . . . . . . . . . . . AVDD + 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND - 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . 0.3 V Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . 7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . 7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital Inputs Except the Data Bus D(7:4) . . . . -0.3 V to DVDD + 0.3 V Data Bus Inputs D(7:4) . . . . . . . -0.3 V to OVDD + 0.3 V Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . 700 mW Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: JA = 91C/W, JC = 30C/W. 48-Lead LFCSP: JC = 26C/W. ORDERING GUIDE Model AD7650AST AD7650ASTRL AD7650ACP1 AD7650ACPRL1 EVAL-AD7650CB2 EVAL-CONTROL BRD23 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description Quad Flatpack (LQFP) Quad Flatpack (LQFP) Quad Flatpack (LFCSP) Quad Flatpack (LFCSP) Package Option ST-48 ST-48 CP-481 CP-481 Evaluation Board Controller Board NOTES 1 Future Product. Contact Factory for availability. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7650 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -5- AD7650 PIN CONFIGURATION 48-Lead LQFP and 48-Lead LFSCP (ST-48 and CP-48) REFGND REF IN+ NC 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 NC 3 DGND 4 OB/2C 5 WARP 6 IMPULSE 7 SER/PAR 8 D0 9 D1 10 D2 11 D3 12 NC = NO CONNECT IN- NC NC NC NC NC NC NC PIN 1 IDENTIFIER 36 35 34 33 32 AGND CNVST PD RESET CS AD7650 TOP VIEW (Not to Scale) RD DGND 29 BUSY 31 30 28 27 26 25 D15 D14 D13 D12 13 14 15 16 17 18 19 20 21 22 23 24 D7/RDC/SDIN OGND D4/EXT/INT DVDD DGND D8/SDOUT PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3, 40-42, 44-48 4 5 Mnemonic AGND AVDD NC DGND OB/2C Type P P Description Analog Power Ground Pin Input Analog Power Pins. Nominally 5 V. No Connect Must be tied to the ground where DVDD is referred. Straight Binary/Binary Two's Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a two's complement output from its internal shift register. Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the state of SER/PAR. When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. -6- REV. 0 DI DI 6 WARP DI 7 8 9-12 13 IMPULSE SER/PAR DATA[0:3] DATA[4] or EXT/INT DI DI DO DI/O 14 DATA[5] or INVSYNC DI/O 15 DATA[6] or INVSCLK DI/O D10/SYNC D11/RDERROR D5/INVSYNC D6/INVSCLK D9/SCLK OVDD AD7650 PIN FUNCTION DESCRIPTIONS (continued) Pin No. 16 Mnemonic DATA[7] or RDC/SDIN Type DI/O Description When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/ INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground Input/Output Interface Digital Power. Nominally at the same supply than the supply of the host interface (5 V or 3 V). Digital Power. Nominally at 5 V. Digital Power Ground When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7650 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as a incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless of the state of SER/PAR. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must Be Tied to Digital Ground Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. Reset Input. When set to a logic HIGH, reset the AD7650. Current conversion if any is aborted. If not used, this pin could be tied to DGND. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 17 18 19 20 21 OGND OVDD DVDD DGND DATA[8] or SDOUT P P P P DO 22 DATA[9] or SCLK DI/O 23 DATA[10] or SYNC DO 24 DATA[11] or RDERROR DO 25-28 29 DATA[12:15] BUSY DO DO 30 31 32 33 34 DGND RD CS RESET PD P DI DI DI DI REV. 0 -7- AD7650 PIN FUNCTION DESCRIPTIONS (continued) Pin No. 35 Mnemonic CNVST Type DI Description Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if CNVST is held low when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Must Be Tied to Analog Ground Reference Input Voltage Reference Input Analog Ground Analog Input Ground Primary Analog Input with a Range of 0 V to VREF. 36 37 38 39 43 AGND REF REFGND IN- IN+ P AI AI AI AI NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power DEFINITION OF SPECIFICATIONS INTEGRAL NONLINEARITY ERROR (INL) TOTAL HARMONIC DISTORTION (THD) Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. DIFFERENTIAL NONLINEARITY ERROR (DNL) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. SIGNAL-TO-NOISE RATIO (SNR) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. FULL-SCALE ERROR SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. SIGNAL TO (NOISE + DISTORTION) RATIO (S/[N+D]) The last transition (from 011 . . . 10 to 011 . . . 11 in two's complement coding) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (2.49994278 V for the 0 V-2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. UNIPOLAR ZERO ERROR S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. APERTURE DELAY Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. TRANSIENT RESPONSE The first transition should occur at a level 1/2 LSB above analog ground (19.073 V for the 0 V-2.5 V range). Unipolar zero error is the deviation of the actual transition from that point. SPURIOUS FREE DYNAMIC RANGE (SFDR) The time required for the AD7650 to achieve its rated accuracy after a full-scale step function is applied to its input. OVERVOLTAGE RECOVERY The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. EFFECTIVE NUMBER OF BITS (ENOB) The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value. ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: ENOB = S N + D ([ ] dB - 1.76 / 6.02 ) and is expressed in bits. -8- REV. 0 Typical Performance Characteristics-AD7650 4 3 2 1 DNL - LSB INL - LSB 7000 3 10000 9000 2 8000 9514 COUNTS 1 0 -1 -2 -3 -4 6000 5000 4000 3000 2000 1000 0 0 79 151 1 0 0 3336 3303 0 -1 -2 0 16384 32768 CODE 49152 65536 -3 0 16384 32768 CODE 49152 65536 0 8003 8005 7FFF 7FFD 8001 7FFE 8000 8004 8006 8002 CODE - Hexa TPC 1. Integral Nonlinearity vs. Code TPC 2. Differential Nonlinearity vs. Code TPC 3. Histogram of 16,384 Conversions of a DC Input at the Code Transition 100 15.0 8000 7000 6000 5000 4000 3000 2000 1000 0 0 0 12 759 0 7353 7396 -20 AMPLITUDE - dB of Full Scale -40 -60 -80 -100 -120 -140 14 0 0 fS = 571kSPS fIN = 45.01kHz SNR AND S/[N+D] - dB SNR = 87dB THD = -96dB SFDR = 98dB SINAD = 86.5dB 95 ENOB 90 SNR 85 SINAD 14.5 14.0 ENOB - Bits COUNTS 13.5 80 13.0 850 75 12.5 -160 7FFE 8002 8004 7FFC 8000 8003 8005 7FFD 7FFF 8001 CODE - Hexa 0 57 114 171 228 FREQUENCY - kHz 285 70 1 100 10 FREQUENCY - kHz 12.0 1k TPC 4. Histogram of 16,384 Conversions of a DC Input at the Code Center TPC 5. FFT Plot TPC 6. SNR, S/(N+D), and ENOB vs. Frequency -60 -65 -70 SFDR 115 110 OPERATING CURRENT - A 105 100 100k AVDD, WARP/NORMAL 10k 1k 100 10 1 0.1 OVDD, ALL MODES 0.01 0.001 0.1 DVDD, WARP/NORMAL AVDD, IMPULSE DVDD, IMPULSE 50 OVDD = 2.7V, 85 C 40 THD, HARMONICS - dB -75 -80 -85 -90 -95 -100 -105 -110 -115 0 10 100 FREQUENCY - kHz 3RD HARMONIC 2ND HARMONIC THD SFDR - dB 95 90 85 80 75 70 65 60 1k t12 DELAY - ns 30 OVDD = 2.7V, 25 C 20 OVDD = 5V, 85 C 10 OVDD = 5V, 25 C 0 1 10 100 1k 10k 100k SAMPLING RATE - SPS 1M 0 50 100 CL - pF 150 200 TPC 7. THD, Harmonics, and SFDR vs. Frequency TPC 8. Operating Currents vs. Sample Rate TPC 9. Typical Delay vs. Load Capacitance CL REV. 0 -9- AD7650 CIRCUIT INFORMATION The AD7650 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (ADC). The AD7650 features different modes to optimize performances according to the applications. In warp mode, the AD7650 is capable of converting 570,000 samples per second (570 kSPS). The AD7650 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7650 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic. It is housed in 48-lead LQFP or in a tiny 48-LFCSP packages that save space and allows flexible configurations as either serial or parallel interface. The AD7650 is pin-to-pin compatible with the AD7664. CONVERTER OPERATION first. The capacitor array and the "dummy" capacitor are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between IN+ and IN- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binaryweighted voltage steps (VREF /2, VREF /4, . . . VREF /65536). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. Modes of Operation The AD7650 features three modes of operations, Warp, Normal, and Impulse. Each of these modes is more suitable for specific applications. The Warp mode allows the fastest conversion rate up to 570 kSPS. However, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. This mode makes the AD7650 ideal for applications where both high accuracy and fast sample rate are required. The normal mode is the fastest mode (500 kSPS) without any limitation about the time between conversions. This mode makes the AD7650 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. It is selected when both IMPULSE and WARP are low. The impulse mode, the lowest power dissipation mode, allows power saving between conversions. When operating at 100 SPS, for example, it typically consumes only 21 W. This feature makes the AD7650 ideal for battery-powered applications. The AD7650 is a successive-approximation analog-to-digital converter based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional "LSB" capacitor. The comparator's negative input is connected to a "dummy" capacitor of the same value as the capacitive DAC array. During the acquisition phase, the common terminal of the array tied to the comparator's positive input is connected to AGND via SWA. All independent switches are connected to the analog input IN+. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on IN+ input. Similarly, the "dummy" capacitor acquires the analog signal on IN- input. When the CNVST input goes low, a conversion phase is initiated. When the conversion phase begins, SWA and SWB are opened IN+ REF REFGND MSB 32,768C 16,384C 4C 2C C C LSB SWA SWITCHES CONTROL BUSY COMP IN- 65,536C SWB CNVST CONTROL LOGIC OUTPUT CODE Figure 3. ADC Simplified Schematic -10- REV. 0 AD7650 Transfer Functions Table I. Output Codes and Ideal Input Voltages Digital Output Code (Hex) Description FSR - 1 LSB FSR - 2 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR Analog Input 2.499962 V 2.499923 V 1.250038 V 1.25 V 1.249962 V 38 V 0V Straight Binary FFFF1 FFFE 8001 8000 7FFF 0001 00002 Two's Complement 7FFF1 7FFE 0001 0000 FFFF 8001 80002 Using the OB/2C digital input, the AD7650 offers two output codings: straight binary and two's complement. The LSB size is VREF /65536, which is about 38.15 V. The ideal transfer characteristic for the AD7650 is shown in Figure 4 and Table I. 1 LSB = V REF /65536 ADC CODE - Straight Binary 111...111 111...110 111...101 NOTES 1 This is also the code for overrange analog input (V IN+ - VIN- above VREF - VREFGND). 2 This is also the code for underrange analog input (V IN+ below V IN-). 000...010 000...001 000...000 0V 1 LSB 0.5 LSB ANALOG INPUT VREF - 1 LSB VREF - 1.5 LSB TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7650. Figure 4. ADC Ideal Transfer Function ANALOG SUPPLY (5V) 100 + 10 F 100nF + 10 F 100nF 100nF + 10 F DIGITAL SUPPLY (3.3V OR 5V) AVDD 2.5V REF NOTE 1 + CREF1 1F REFGND AGND DGND DVDD OVDD OGND SCLK SERIAL PORT REF SDOUT BUSY AD7650 NOTE 2 ANALOG INPUT (0V TO 2.5V) U1 CC 15 IN+ 4.7nF IN- PD RESET CS RD CNVST D NOTE 3 C/ P/DSP OB/2C SER/PAR WARP IMPULSE CLOCK DVDD NOTES 1. THE ADR421 IS RECOMMENDED WITH CREF = 47 F. 2. THE AD8021 IS RECOMMENDED WITH A COMPENSATION CAPACITOR CC = 10pF, TYPE CERAMIC NPO. 3. OPTIONAL LOW JITTER CNVST. Figure 5. Typical Connection Diagram REV. 0 -11- AD7650 Analog Input Figure 6 shows an equivalent circuit of the input structure of the AD7650. AVDD D1 IN+ OR IN- C1 R1 C2 * The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7650. The noise coming from the driver is filtered by the AD7650 analog input circuit one-pole low-pass filter made by R1 and C2 or the external filter if any are used. * The driver needs to have a THD performance suitable to that of the AD7650. The AD8021 meets these requirements and is usually appropriate for almost all applications. The AD8021 needs an external compensation capacitor of 10 pF. This capacitor should have good linearity as an NPO ceramic or mica type. The AD8022 could also be used where dual version is needed and gain of 1 is used. The AD829 is another alternative where high-frequency (above 100 kHz) performance is not required. In gain of 1, it requires an 82 pF compensation capacitor. The AD8610 is another option where low bias current is needed in low-frequency applications. Voltage Reference Input D2 AGND Figure 6. Equivalent Analog Input Circuit The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN-. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V. This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forwardbiased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer's (U1) supplies are different from AVDD. In such case, an input buffer with a short circuit current limitation can be used to protect the part. This analog input structure allows the sampling of the differential signal between IN+ and IN-. Unlike other converters, the IN- input is sampled at the same time as the IN+ input. By using this differential input, small signals common to both inputs are rejected. For instance, by using IN- to sense a remote signal ground, difference of ground potentials between the sensor and the local ADC ground are eliminated. During the acquisition phase, the impedance of the analog input IN+ can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. Capacitor C1 is primarily the pin capacitance. The resistor R1 is typically 140 and is a lumped component made up of some serial resistors and the on resistance of the switches. The capacitor C2 is typically 60 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C1. The R1, C2 makes a onepole low-pass filter that reduces undesirable aliasing effect and limits the noise. When the source impedance of the driving circuit is low, the AD7650 can be driven directly. Large source impedances will significantly affect the ac performances, especially the total harmonic distortion. Driver Amplifier Choice The AD7650 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7650 has a dynamic input impedance. Therefore, it should be driven by a low impedance source with an efficient decoupling between REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. 47 F is an appropriate value for tantalum capacitor when used with one of the recommended reference voltages: * The low-noise, low temperature drift ADR421 and AD780 voltage references. * The low-power ADR291 voltage reference. * The low-cost AD1582 voltage reference. For applications using multiple AD7650s, it is more effective to buffer the reference voltage with a low-noise, very stable op amp such as the AD8031. Care should also be taken with the reference temperature coefficient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. For instance, a 15 ppm/C tempco of the reference changes the full scale by 1 LSB/C. Note that VREF , as mentioned in the specification table, could be increased to AVDD -1.85 V. Since the input range is defined in terms of VREF, this would essentially increase the range to make it a 0 V to 3 V input range with a reference voltage of 3 V. The AD780 can be selected with a 3 V reference voltage. Power Supply Although the AD7650 is easy to drive, the driver amplifier needs to meet at least the following requirements: * The driver amplifier and the AD7650 analog input circuit must be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). In the amplifier's data sheet, the settling at 0.1% to 0.01% is more commonly specified. It could significantly differ from the settling time at 16-bit level and it should therefore be verified prior to the driver selection. The tiny op amp AD8021, which combines ultralow noise and a high-gain bandwidth, meets this settling time requirement even when used with high gain up to 13. The AD7650 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 5. The AD7650 is independent of power supply sequencing and thus free from supply voltage induced latchup. -12- REV. 0 AD7650 POWER DISSIPATION VS. THROUGHPUT Operating currents are very low during the acquisition phase, which allows a significant power saving when the conversion rate is reduced as shown in Figure 7. This power saving depends on the mode used. In impulse mode, the AD7650 automatically reduces its power consumption at the end of each conversion phase. This feature makes the AD7650 ideal for very low power battery applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power supply rails (i.e., DVDD or DGND for all inputs except EXT/INT, INVSYNC, INVSCLK, RDC/SDIN, and OVDD or OGND for these last four inputs). 100k WARP/NORMAL 10k power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7650 could sometimes run slightly faster then the guaranteed limits in the impulse mode of 444 kSPS. This feature does not exist in warp or normal modes. t9 RESET BUSY DATA t8 CNVST Figure 9. RESET Timing POWER DISSIPATION - W 1k 100 IMPULSE 10 Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. It is a good thing to shield the CNVST trace with ground and also to add a low value serial resistor (i.e., 50 V) termination close to the output of the component that drives this line. For applications where the SNR is critical, CNVST signal should have a very low jitter. Some solutions to achieve that is to use a dedicated oscillator for CNVST generation or, at least, to clock it with a high-frequency low-jitter clock as shown in Figure 5. DIGITAL INTERFACE 1 0.1 0.1 1 10 100 1k 10k SAMPLING RATE - SPS 100k 1M Figure 7. Power Dissipation vs. Sampling Rate CONVERSION CONTROL Figure 8 shows the detailed timing diagrams of the conversion process. The AD7650 is controlled by the signal CNVST which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. t2 t1 CNVST The AD7650 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7650 digital interface also accommodates both 3 V or 5 V logic by simply connecting the OVDD supply pin of the AD7650 to the host system interface digital supply. Finally, by using the OB/2C input pin, both two's complement or straight binary coding can be used. The two signals CS and RD control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7650 in multicircuits applications and is held low in a single AD7650 design. RD is generally used to enable the conversion result on the data bus. CS = RD = 0 BUSY t4 t3 t5 t6 CONVERT ACQUIRE CONVERT BUSY CNVST t1 MODE ACQUIRE t 10 t4 t3 DATA BUS t7 t8 Figure 8. Basic Conversion Timing t 11 PREVIOUS CONVERSION DATA NEW DATA In impulse mode, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7650 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7650 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at Figure 10. Master Parallel Data Timing for Reading (Continuous Read) REV. 0 -13- AD7650 PARALLEL INTERFACE CS = 0 CNVST, RD The AD7650 is configured to use the parallel interface when the SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figure 11 and Figure 12. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. CS t1 BUSY t4 t3 DATA BUS PREVIOUS CONVERSION t 12 t 13 Figure 12. Slave Parallel Data Timing for Reading (Read During Convert) RD SERIAL INTERFACE BUSY The AD7650 is configured to use the serial interface when the SER/PAR is held high. The AD7650 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on SCLK pin. The output data is valid on both the rising and falling edge of the data clock. CURRENT CONVERSION DATA BUS t 12 t 13 MASTER SERIAL INTERFACE Internal Clock Figure 11. Slave Parallel Data Timing for Reading (Read After Convert) The AD7650 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7650 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 13 and Figure 14 show the detailed timing diagrams of these two modes. CS, RD EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 t3 CNVST BUSY t 28 t 30 t 29 SYNC t 25 t 18 t 19 t 20 t 21 1 2 3 14 15 t 14 t 24 16 t 26 SCLK t 15 t 27 SDOUT X D15 D14 D2 D1 D0 t 16 t 22 t 23 Figure 13. Master Serial Data Timing for Reading (Read After Convert) -14- REV. 0 AD7650 EXT/INT = 0 CS, RD RDC/SDIN = 1 INVSCLK = INVSYNC = 0 t1 CNVST t3 BUSY t 17 SYNC t 25 t 19 t 20 t 21 t 24 2 3 14 15 16 t 14 SCLK t 15 t 18 t 26 1 t 27 SDOUT X D15 D14 D2 D1 D0 t 16 t 22 t 23 Figure 14. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Usually, because the AD7650 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used. In read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimize potential feedthrough between digital activity and the critical conversion decisions. In read-after-conversion mode, it should be noted that, unlike in other modes, the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer BUSY width. SLAVE SERIAL INTERFACE External Clock discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 15 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS and RD are low. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is to be able to read the data at any speed up to 40 MHz, which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7650 provides a "daisy-chain" feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 17. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite to the one used to shift out the data on SDOUT. Hence, the MSB of the "upstream" converter just follows the LSB of the "downstream" converter on the next SCLK cycle. The AD7650 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 15 and Figure 16 show the detailed timing diagrams of these methods. While the AD7650 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7650 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a REV. 0 -15- AD7650 CS EXT/INT = 1 INVSCLK = 0 RD = 0 BUSY t 35 t 36 t 37 SCLK 1 2 3 14 15 16 17 18 t 31 SDOUT X D15 t 32 D14 D13 D1 D0 X15 X14 t 16 SDIN t 34 X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 15. Slave Serial Data Timing for Reading (Read After Convert) CS EXT/INT = 1 INVSCLK = 0 RD = 0 CNVST BUSY t3 t 35 t 36 t 37 1 2 3 14 15 16 SCLK t 31 SDOUT X D15 t 32 D14 D13 D1 D0 t 16 Figure 16. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) External Clock Data Read During Conversion BUSY OUT BUSY BUSY AD7650 #2 (UPSTREAM) RDC/SDIN SDOUT CNVST CS SCLK AD7650 #1 (DOWNSTREAM) RDC/SDIN SDOUT CNVST CS SCLK DATA OUT Figure 16 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are both low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. The 16 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no "daisy chain" feature in this mode and RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock of, at least 18 MHz, when impulse mode is used, 25 MHz when normal mode is used or 40 MHz when warp mode is used, is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. That allows the use of a slower clock speed like 14 MHz in impulse mode, 18 MHz in normal mode and 25 MHz in warp mode. SCLK IN CS IN CNVST IN Figure 17. Two AD7650s in a "Daisy-Chain" Configuration -16- REV. 0 AD7650 MICROPROCESSOR INTERFACING ADSP-21065L in Master Serial Interface The AD7650 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7650 is designed to interface either with a parallel 16-bit-wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7650 to prevent digital noise from coupling into the ADC. The following sections illustrate the use of the AD7650 with an SPI-equipped microcontroller, the ADSP-21065L and ADSP-218x signal processors. SPI Interface (MC68HC11) As shown in Figure 19, the AD7650 can be interfaced to the ADSP-21065L using the serial interface in master mode without any glue logic required. This mode combines the advantages of reducing the number of wire connections and being able to read the data during or after conversion at user convenience. The AD7650 is configured for the internal clock mode (EXT/INT low) and acts, therefore, as the master device. The convert command can be generated by either an external low jitter oscillator or, as shown, by a FLAG output of the ADSP-21065L or by a frame output TFS of one serial port of the ADSP-21065L which can be used as a timer. The serial port on the ADSP-21065L is configured for external clock (IRFS = 0), rising edge active (CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial port of the ADSP-21065L is configured by writing to its receive control register (SRCTL)--see ADSP-2106x SHARC User's Manual. Because the serial port within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. DVDD OVDD OR OGND Figure 18 shows an interface diagram between the AD7650 and an SPI-equipped microcontroller like the MC68HC11. To accommodate the slower speed of the microcontroller, the AD7650 acts as a slave device and data must be read after conversion. This mode allows also the "daisy chain" feature. The convert command could be initiated in response to an internal timer interrupt. The reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conversion signal (BUSY going low) using to an interrupt line of the microcontroller. The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI Interrupt Enable (SPIE = 1) by writing to the SPI Control Register (SPCR). The IRQ is configured for edge-sensitive-only operation (IRQE = 1 in OPTION register). DVDD OVDD SER/PAR EXT/INT AD7650* SER/PAR RDC/SDIN RD EXT/INT SYNC SDOUT SCLK CNVST ADSP-21065L* SHARC RFS DR RCLK FLAG OR TFS AD7650* MC68HC11* CS INVSYNC INVSCLK *ADDITIONAL PINS OMITTED FOR CLARITY BUSY CS RD INVSCLK SDOUT SCLK CNVST IRQ MISO/SDI SCK I/O PORT Figure 19. Interfacing to the ADSP-21065L Using the Serial Master Mode *ADDITIONAL PINS OMITTED FOR CLARITY Figure 18. Interfacing the AD7650 to SPI Interface REV. 0 -17- AD7650 APPLICATION HINTS Bipolar and Wider Input Ranges should still be made at one point only, a star ground point, which should be established as close as possible to the AD7650. It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7650 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supplies lines to the AD7650 should use as large trace as possible to provide low impedance paths and reduce the effect of glitches on the power supplies lines. Good decoupling is also important to lower the supplies impedance presented to the AD7650 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supplies pins AVDD, DVDD, and OVDD close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 F capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7650 can either be a separate supply or come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended that if no separate supply is available, connect the DVDD digital supply to the analog supply, AVDD, through an RC filter as shown in Figure 5, and connect the system supply to the interface digital supply, OVDD, and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. The AD7650 has five different ground pins: IN-, REFGND, AGND, DGND, and OGND. IN- is used to sense the analog input signal. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. Evaluating the AD7650 Performance In some applications, it is desired to use a bipolar or wider analog input range like, for instance, 10 V, 5 V or 0 V to 5 V. Although the AD7650 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. Figure 20 shows a connection diagram which allows that. Components values required and resulting full-scale ranges are shown in Table II. R1 R2 U1 5V 10nF IN+ ANALOG INPUT AD7650 U2 R3 R4 100nF IN- 2.5V REF CREF 1mF REFGND REF Figure 20. Using the AD7650 in 16-Bit Bipolar and/or Wider Input Ranges Table II. Component Values and Input Ranges Input Range 10 V 5 V 0 V to -5 V R1 250 500 1 k R2 2 k 2 k 2 k R3 10 k 10 k None R4 8 k 6.67 k 0 For applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer, U2, as shown for bipolar input ranges in Figure 20. Layout The AD7650 has very good immunity to noise on the power supplies as can be seen in Figure 9. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7650 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7650 or, at least, as close as possible to the AD7650. If the AD7650 is in a system where multiple devices require analog-to-digital ground connections, the connection A recommended layout for the AD7650 is outlined in the evaluation board for the AD7650. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the Eval-Control Board. -18- REV. 0 AD7650 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 1 0.354 (9.00) BSC SQ 48 37 36 TOP VIEW (PINS DOWN) 0.276 (7.00) BSC SQ 25 COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09) 08 MIN 12 13 24 0.019 (0.5) 0.011 (0.27) BSC 0.006 (0.17) 7 0 0.006 (0.15) SEATING 0.002 (0.05) PLANE 0.057 (1.45) 0.053 (1.35) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 48-Lead Frame Chip Scale Flatpack (LFCSP) (CP-48) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 37 0.009 (0.24) 36 0.276 (7.0) BSC SQ 48 1 PIN 1 INDICATOR TOP VIEW 0.266 (6.75) BSC SQ BOTTOM VIEW 0.215 (5.45) 0.209 (5.30) SQ 0.203 (5.15) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 128 MAX 0.031 (0.80) MAX 0.026 (0.65) NOM 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) 25 24 1 13 2 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) PADDLE CONNECTED TO AGND 0.039 (1.00) MAX 0.033 (0.85) NOM 0.020 (0.50) BSC 0.008 (0.20) REF CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. 0 -19- -20- C02770-0-1/02(0) PRINTED IN U.S.A. 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